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 HD74LVC00
Quad. 2-input NAND Gates
REJ03D0341-0300Z (Previous ADE-205-060B (Z)) Rev.3.00 Jul. 22, 2004
Description
The HD74LVC00 has four 2-input NAND gates in a 14 pin package. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation.
Features
* * * * * * VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 24 mA (@VCC = 3.0 V to 5.5 V) Ordering Information
Package Type SOP-14 pin (JEITA) TSSOP-14 pin Package Code FP-14DAV TTP-14DV Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel)
Part Name HD74LVC00FPEL HD74LVC00TELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs A L L H H H: L: High level Low level B L H L H Output Y H H H L
Rev.3.00 Jul. 22, 2004 page 1 of 5
HD74LVC00
Pin Arrangement
1A 1 1B 1Y 2 3
14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y
2A 4 2B 2Y 5 6
GND 7
(Top view)
Absolute Maximum Ratings
Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg Ratings -0.5 to 6.0 -50 -0.5 to 6.0 -50 50 -0.5 to VCC+0.5 50 100 -65 to +150 Unit V mA V mA mA V mA mA C Conditions VI = -0.5 V VO = -0.5 V VO = VCC+0.5 V
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Output current Symbol VCC VI VO Ta IOH IOL Input rise / fall time *1 tr, tf Ratings 1.5 to 5.5 2.0 to 5.5 0 to 5.5 0 to VCC -40 to 85 -12 -24*2 12 24*2 10 Unit V V C mA Conditions Data retention At operation A, B Y VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 2.7 V VCC = 3.0 V to 5.5 V
ns/V
Notes: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
2. Duty cycle 50%.
Rev.3.00 Jul. 22, 2004 page 2 of 5
HD74LVC00
Electrical Characteristics
Ta = -40 to 85C Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 5.5 3.0 to 3.6 Min 2.0 VCCx0.7 -- -- VCC-0.2 2.2 2.4 2.0 3.8 -- -- -- -- -- -- -- Max -- -- 0.8 VCCx0.3 -- -- -- -- -- 0.2 0.4 0.55 0.55 5.0 20 500 Unit V Test Conditions
V
IOH = -100 A IOH = -12 mA IOH = -24 mA
VOL
V
IOL = 100 A IOL = 12 mA IOL = 24 mA VIN = 5.5 V or GND VIN = VCC or GND VIN = one input at (VCC-0.6)V, other inputs at VCC or GND
Input current Quiescent supply current
IIN ICC ICC
A A A
Switching Characteristics
Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL CIN CO VCC (V) 2.7 3.30.3 5.00.5 2.7 2.7 Min -- 1.5 -- -- -- Typ 4.5 3.5 3.0 3.0 15.0 Max 7.0 6.0 5.5 -- -- Unit ns From (Input) A or B To (Output) Y
Input capacitance Output capacitance
pF pF
Test Circuit
Input VCC VCC
Pulse Generator Zout = 50 CL = 50 pF Output 450 50 Scope
Note:
1. CL includes probe and jig capacitance.
Rev.3.00 Jul. 22, 2004 page 3 of 5
HD74LVC00 Waveforms
tr Input A or B 10 % t PHL Output Y 90 % Vref 90 % Vref 10 % t PLH VOH Vref Vref VOL tf VIH GND
TEST VIH Vref
VCC = 2.7 V, 3.30.3 V VCC = 5.00.5 V 2.7 V VCC 1.5 V 50%VCC
Notes:
1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform : PRR = 10 MHz, duty cycle 50%
Rev.3.00 Jul. 22, 2004 page 4 of 5
HD74LVC00
Package Dimensions
As of January, 2003
Unit: mm
10.06 10.5 Max 14 8
1
7
5.5
*0.20 0.05
2.20 Max
0.20 7.80 + 0.30 -
1.42 Max
1.15 0 - 8 0.70 0.20
1.27 *0.40 0.06
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g
*Ni/Pd/Au plating
0.10 0.10
0.15
As of January, 2003
Unit: mm
5.00 5.30 Max 14 8
1
7 0.65 1.0 0.13 M 6.40 0.20 0.83 Max 0 - 8 0.50 0.10
*0.20 0.05
4.40
*0.15 0.05
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-14DV -- -- 0.05 g
Rev.3.00 Jul. 22, 2004 page 5 of 5
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
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http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0


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